The present invention relates generally to semiconductor manufacturing and, more particularly, to forming fins in FinFET devices.
The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require design features, such as gate lengths, below 100 nanometers (nm), high reliability, and increased manufacturing throughput. The reduction of design features below 100 nm challenges the limitations of conventional methodology.
For example, when the gate length of conventional planar metal oxide semiconductor field effect transistors (MOSFETs) is scaled below 100 nm, problems associated with short channel effects, such as excessive leakage between the source and drain, become increasingly difficult to overcome. In addition, mobility degradation and a number of process issues also make it difficult to scale conventional MOSFETs to include increasingly smaller device features. New device structures are therefore being explored to improve FET performance and allow further device scaling.
Double-gate MOSFETs represent new structures that have been considered as candidates for succeeding existing planar MOSFETs. In double-gate MOSFETs, two gates may be used to control short channel effects. A FinFET is a double-gate structure that exhibits good short channel behavior. A FinFET includes a channel formed in a vertical fin. The FinFET structure may be fabricated using layout and process techniques similar to those used for conventional planar MOSFETs.
Implementations consistent with the principles of the invention form multiple fins in FinFET devices. By using spacers for forming the fins, narrow fins may be formed beyond the limits of lithography.
In accordance with the purpose of this invention as embodied and broadly described herein, a method for forming fins in a FinFET is provided. The method includes forming an oxide layer on a silicon on insulator (SOI) wafer, creating at least one opening in the oxide layer, forming silicon in the at least one opening, etching the silicon to form spacers, the spacers being adjacent sidewalls of the opening, and removing the oxide layer and silicon located below the oxide layer to form the fins.
In another implementation consistent with the present invention, a method of manufacturing a semiconductor device is provided. The method includes depositing an oxide layer over a conductive layer, where the conductive layer includes conductive material. The method further includes etching at least one opening in the oxide layer, where the at least one opening has two sidewalls, filling the at least one opening with the conductive material, forming spacers adjacent the two sidewalls of the at least one opening, removing the oxide layer and a portion of the conductive layer to form fin structures, forming a source region and a drain region, depositing a gate material over the fin structures, and patterning and etching the gate material to form at least one gate electrode.
In yet another implementation consistent with the principles of the invention, a method for forming a group of structures on a wafer including a conductive layer that includes conductive material is provided. The method includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, forming an oxide layer over the conductive layer, etching at least one opening in the oxide layer, filling the at least one opening with the conductive material, etching the conductive material to form spacers along sidewalls of the at least one opening, and removing the oxide layer and a portion of the conductive layer to form the group of structures.